Engineer, ASIC Physical Design at PrimeSilicon Technology (BD) Ltd
A simple individual with a knack for tackling challenging tasks, navigating the dynamic field of ASIC physical design. Passionate about technology, with a focus on learning and improving constantly.
PrimeSilicon Technology (BD) Ltd | Sep 2022 – Present
- Working with Cadence Innovus and OpenROAD to implement PnR for custom designs.
- Utilizing data mining to analyze and optimize design flow efficiency.
- Performing full-chip physical implementation from RTL to GDSII, including floorplanning, CTS, routing, and timing closure.
Bachelor's in Electrical Engineering, Chittagong University of Engineering and Technology (2022)
7 nm Technology RISC-V Architecture Custom Chip: Led the physical design and implementation of a custom RISC-V processor using 7nm technology, optimizing performance and power efficiency.